Modern high-performance digital chips, such as microprocessors, often employ a single-phase clock for sequencing of internal events. Such clocks provide for two timing edges per cycle: the clock rising edge and the clock falling edge. Large on-chip memories, such as caches, often need more sequence control-timing edges than are provided by a single-phase system clock.
Prior art efforts to generate more timing edges than the system clock provides revolve around circuit and device-characteristic dependent delay chains, so-called “self-timed” circuits. These delay chains typically comprise a set of serially connected inverters, with individual tap lines connected between the inverters. The delay caused by each inverter produces a phase-delayed signal on the tap line attached to the output of the inverter.
Delay chains of this type sometimes use capacitive loading to control the generation of the multi-phase signals. In particular, parallel-connected capacitors are tied to the output of an inverter in the delay chain. There are known prior art techniques to control this capacitive loading using analog voltages. Thus, for example, a continuously variable voltage can be used to control current into a fixed capacitance. Alternately, a continuously variable voltage can be used to control a variable capacitance. Unfortunately, these approaches are expensive to implement for two reasons. First, they require a very quiet voltage source. Second, they require large area filter capacitors.
It is also known to control the loading associated with a fixed capacitance through the use of digitally switched current. There are several problems with this approach. First, it is difficult to produce a linear response in a MOS semiconductor application. In addition, this approach has limited resolution in MOS semiconductor applications.
It is also known to vary the number of identical delay stages (e.g., inverters) through digital control. Switching delay stages in and out of the delay chain provides only course timing control and therefore is not practical in many applications.
A characteristic of self-timed circuits of this type is that they are independent of the system clock. At times this can be a disadvantage, particularly when the sequence control timing edge provided by the self-timed circuit is incorrectly positioned.
In view of the foregoing, it would be desirable to provide a technique for generating multi-phase signals that operates responsive to the system clock. It would be desirable to provide a digital design utilizing a digital control circuit and digital control signals. Such a design should be relatively inexpensive, unlike analog control implementations. A design of this type should also provide a linear response and high resolution.